Tree-Based Partitioning Approach for Network-on-Chip Synthesis

Since most System-on-Chips (SoCs) consist of heterogeneous IP core(s), application-specific Network on Chip (NoC) architectures are appropriate to meet the design requirements. The energy and performance optimization in the NoC design will continue to be the main design goal in nanoscale technologie...

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Bibliographic Details
Published in2011 12th International Conference on Computer-Aided Design and Computer Graphics pp. 465 - 470
Main Authors Binjie Song, Shan Zeng, Yuchun Ma, Ning Xu, Yu Wang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2011
Subjects
Algorithm design and analysis
Estimation
Network interfaces
Network topology
NoC
partition
Partitioning algorithms
power
Power demand
synthesis
Topology
tree
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ISBN145771079X
9781457710797
DOI10.1109/CAD/Graphics.2011.20

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Summary:Since most System-on-Chips (SoCs) consist of heterogeneous IP core(s), application-specific Network on Chip (NoC) architectures are appropriate to meet the design requirements. The energy and performance optimization in the NoC design will continue to be the main design goal in nanoscale technologies. In this paper, we present a new hierarchal partitioning approach considering not only the reduction of wire length among cores, but also the optimization of switching power consumption subject to performance constraints. The experimental results on different benchmarks showed that our NoC topology synthesis algorithm can effectively save power and improve performance.
ISBN:145771079X
9781457710797
DOI:10.1109/CAD/Graphics.2011.20