Implementation of Static and Semi-Static Versions of a 24+8×8 Quad-Rail NULL Convention Multiply and Accumulate Unit

• Published in: 2007 IEEE Region 5 Technical Conference pp. 53 - 58
• Main Authors: Mallepalli, S.R., Kakarla, S., Burugapalli, S., Beerla, S., Kotla, S., Sunkara, P., Al-Assadi, W.K., Smith, S.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2007
• Subjects: Algorithm design and analysis; Boolean functions; Clocks; CMOS logic circuits; CMOS process; Delay; Logic circuits; Logic design; Rails; Wires
• ISBN: 142441279X; 9781424412792
• DOI: 10.1109/TPSD.2007.4380351

This paper focuses on implementing an unsigned 24+8x8 quad-rail (i.e., accumulator consists of 12 quad-rail signals, while the multiplier and multiplicand are each 4 quad-rail signals) multiply and accumulate (MAC) unit using the asynchronous NULL convention logic (NCL) paradigm. The design utilizes the array-structured algorithm for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8 V 0.18 mum TSMC CMOS process. The MAC is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.