A Hardware Threat Modeling Concept for Trustable Integrated Circuits

Similar to the effects of software viruses, hardware can also be compromised by introduction of malicious logic into circuits to cause unwanted system behaviors. This can be done by changing or adding internal logic, in such a way that it is undetectable using traditional testing and verification to...

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Bibliographic Details
Published in2007 IEEE Region 5 Technical Conference pp. 354 - 357
Main Authors Jia Di, Smith, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2007
Subjects
Design automation
Design engineering
Fabrication
Field programmable gate arrays
Hardware
Integrated circuit modeling
Logic circuits
Logic design
Logic testing
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ISBN142441279X
9781424412792
DOI10.1109/TPSD.2007.4380353

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Summary:Similar to the effects of software viruses, hardware can also be compromised by introduction of malicious logic into circuits to cause unwanted system behaviors. This can be done by changing or adding internal logic, in such a way that it is undetectable using traditional testing and verification tools and techniques. Therefore, the user of the circuit needs to decide whether it can be trusted, i.e., it only performs functions defined in the original circuit specification (no more and no less), before employing it in the system. In this paper, a preliminary methodology is proposed to model potential hardware threats in order to determine a circuit's trustability and provide guidance to malicious-logic checking tools.
ISBN:142441279X
9781424412792
DOI:10.1109/TPSD.2007.4380353