TCAD based study of a novel 24 nm quantum well symmetric IDG NMOS transistor with ultra-low Ioff

• Published in: International Conference for Convergence for Technology-2014 pp. 1 - 6
• Main Authors: Baishya, S., Deb, Soumen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2014
• Subjects: back gate biasing techniques; buried back gate; Doping; FD SOI; GIBL effect; IDG MOS; isotype Heterostructure; Junctions; Logic gates; Metals; MOS devices; Performance evaluation; quantum confinement; quantum well; Silicon; suface mobility
• DOI: 10.1109/I2CT.2014.7092215

This paper presents the design of a 24 nm symmetric Hetero Channel Si Independent Double Gate (IDG) NMOS transistor with Ge/Si/Ge channel structure (forming a Quantum Well in lateral direction), with elevated Si S/D Structure (also called Raised and Digged S/D Structure), n + polysilicon as front and back gate material (Buried Back Gate Structure), High-K Si 3 N 4 spacer in order to suppress SCE's. The dc parameters of the device such as I on , I off , I on /I off ratio, subthreshold swing were evaluated for different back gate biasing and I off and subthreshold swing were found to be optimum at back gate biasing of -0.6 V. The effect different front gate metals was also evaluated using TCAD simulations and it is observed that Molybdenum serves as an excellent front gate metal with extremely low I off ~ 2 pA/μm at back gate biasing of -0.6 V and subthreshold swing of ~ 135 mV/decade at back gate biasing of 0 V, with quite low I on ~ 5×10 -7 A/μm. To improve the on current an undoped channel structure is incorporated with the proposed QW IDG NMOS device, with a slight degradation of I off as well as subthreshold swing. The on current is further enhanced by modulating the width of Si-QW in the channel, and it is found that Si-QW of width 11 nm provides optimum dc performance with I on ~ 2.02×10 -5 A/μm, I off ~ 0.89243 pA/μm and a subthreshold swing of ~108 mV/decade for the back gate biasing voltage of -0.8 V.