Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

• Published in: 2011 International Conference on Reconfigurable Computing and FPGAs pp. 242 - 248
• Main Authors: Salman, A., Rogawski, M., Kaps, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2011
• Subjects: Field programmable gate arrays; Hardware; Internet; IPSec; Partial reconfiguration; Protocols; Security; Software; Throughput; Xilinx FPGA
• ISBN: 9781457717345; 1457717344
• ISSN: 2325-6532
• DOI: 10.1109/ReConFig.2011.33

In this paper we present a practical low-end embedded system solution for Internet Protocol Security (IPSec) implemented on the smallest Xilinx Field Programmable Gate Array (FPGA) device in the Virtex 4 family. The proposed solution supports the three main IPSec protocols: Encapsulating Security Payload (ESP), Authentication Header (AH) and Internet Key Exchange (IKE). This system uses efficiently hardware-software co-design and partial reconfiguration techniques. Thanks to utilization of both methods we were able to save a significant portion of hardware resources with a relatively small penalty in terms of performance. In this work we propose a division of the basic mechanisms of IPSec protocols, namely cryptographic algorithms and their modes of operation to be implemented either in software or hardware. Through this, we were able to combine the high performance offered by a hardware solution with the flexibility of a software implementation. We show that a typical IPSec protocol configuration can be combined with Partial Reconfiguration techniques in order to efficiently utilize hardware resources.