Efficient design of different forms of FIR filter

• Published in: 2014 International Conference on Recent Trends in Information Technology pp. 1 - 4
• Main Authors: Bharti, Deepshikha, Gupta, Kumari Nidhi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2014
• Subjects: Adders; Algorithm design and analysis; Band-pass filters; Delays; DSP; Finite impulse response filters; FIR filter design; Parallel adder; Parallel multiplier; Registers; VLSI design
• DOI: 10.1109/ICRTIT.2014.6996204

Although a number of efficient and high-level design algorithms have been put forward for the realization of FIR filter using the least number of arithmetic operations, but they do not take into account the low-level implementation issues which can exactly make a difference to the area and delay in designing of FIR filter. In this paper, at first, we have presented the delay efficient addition and multiplication architectures that are used in designing of the filter operation. Here We have used an algorithm for the multiplication that reduces the bit width and then an efficient parallel adder is been used that implements the two form of FIR filter with very less amount of delay considering the cost of each operation too. The paper presents two different types of FIR filter with 8 and 16 tap among which one of the form is good for the speed and the other is good for the area.