MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor

• Published in: 2011 International Conference on Reconfigurable Computing and FPGAs pp. 204 - 210
• Main Authors: Varchola, M., Guneysu, T., Mischke, O.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2011
• Subjects: Computer architecture; Delta modulation; Elliptic curve cryptography; Field programmable gate arrays; Hardware; NIST; NIST Primes
• ISBN: 9781457717345; 1457717344
• ISSN: 2325-6532
• DOI: 10.1109/ReConFig.2011.61

In this paper we present compact FPGA-based architectures for standardized elliptic curve cryptography over prime fields. Our approach differs from the many previous works due to the following design principles: First, we minimized storage by efficiently using block memories instead of registers, and second, we focused on elliptic curves based on standardized NIST primes. Furthermore, the presented MicroECC processors are optimized for two goals: a first architecture utilizes a 16-bit data path and a single 16-bit hardware multiplier and is optimized for minimal FPGA resource consumption. The second processor design employs a 32-bit data path and several hardware multipliers for improved throughput. Both implementations are not fixed to a single curve and support point multiplications for (but not limited to) both NIST curves P-256 and P-224. Tested on Xilinx and Micro semi FPGAs, our ECC-P256 processors provide a significantly better performance-per-slice ratio (i.e., a factor of 7.1 and 6.3 for the 16-bit and 32-bit architecture, respectively) compared to a comparable implementation, recently presented on ASAP 2010.