Floating-point division and square root using a Taylor-series expansion algorithm

• Published in: 2007 50th Midwest Symposium on Circuits and Systems pp. 305 - 308
• Main Authors: Taek-Jun Kwon, Sondeen, J., Draper, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2007
• Subjects: Algorithm design and analysis; Application software; Concurrent computing; Delay; Embedded computing; Floating-point arithmetic; Hardware; Iterative algorithms; Microprocessors; Throughput
• ISBN: 1424411750; 9781424411757
• ISSN: 1548-3746
• DOI: 10.1109/MWSCAS.2007.4488594

Hardware support for floating-point (FP) arithmetic is a mandatory feature of modern microprocessor design. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important in many modern applications. Therefore, overall performance can be greatly affected by the algorithms and the implementations used for designing FP-div and FP-sqrt units. In this paper, a fused floating-point multiply/divide/square root unit based on Taylor-series expansion algorithm is proposed. We extended an existing multiply/divide fused unit to incorporate the square root function with little area and latency overhead since Taylor's theorem enables us to compute approximations for many well-known functions with very similar forms. The proposed arithmetic unit exhibits a reasonably good area- performance balance.