Analysis of subthreshold leakage reduction in CMOS digital circuits

• Published in: 2007 50th Midwest Symposium on Circuits and Systems pp. 1400 - 1404
• Main Authors: Deepaksubramanyan, B.S., Nunez, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2007
• Subjects: Batteries; Cellular phones; Circuit optimization; CMOS digital integrated circuits; CMOS technology; Design automation; Digital circuits; Personal digital assistants; Power dissipation; Subthreshold current
• ISBN: 1424411750; 9781424411757
• ISSN: 1548-3746
• DOI: 10.1109/MWSCAS.2007.4488809

Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques have been proposed that efficiently minimize this leakage power loss. A comprehensive survey and analysis of various subthreshold leakage power reduction techniques that are applicable to current battery operated devices is presented in this work with an emphasis on static CMOS circuits. Results show a clear tradeoff between leakage power and other circuit performance parameters. Based on this analysis, a designer or an automation tool would be able to select the appropriate leakage control technique for a particular application.