An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

• Published in: Proceedings / Electronic Components Conference pp. 1853 - 1856
• Main Authors: Sue-Chen Liao, Erh-Hao Chen, Chien-Chou Chen, Shang-Chun Chen, Jui-Chin Chen, Po-Chih Chang, Yiu-Hsiang Chang, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao, Young Suk Kim, Maeda, Nobuhide, Kodama, Shoichi, Kitada, Hideki, Fujimoto, Koji, Ohba, Takayuki
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2014
• Subjects: Etching; Plasmas; Resistance; Silicon; Stacking; Through-silicon vias
• ISSN: 0569-5503
• DOI: 10.1109/ECTC.2014.6897552

An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked wafers was electrically connected without bump electrodes. The improved process such as chemical mechanical planarization (CMP) of Cu re-distribution layer (RDL) is also developed successfully to provide uniform and straight line resistance distribution and reduce the loading of TSV over-etching to avoid the interconnect open issue.