Accelerating Machine Learning Kernel in Hadoop Using FPGAs

• Published in: 2015 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing pp. 1151 - 1154
• Main Authors: Neshatpour, Katayoun, Malik, Maria, Homayoun, Houman
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2015
• Subjects: Acceleration; Big data; Computer architecture; Field programmable gate arrays; FPGA; Hardware; Kernel; Machine learning algorithms
• DOI: 10.1109/CCGrid.2015.165

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. % Considering the time dedicated to create such specialized architectures, a model that estimates the potential speedup achievable through offloading various parts of the algorithm to specialized hardware would be necessary. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Signboards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment.