Efficient bi-level reconfiguration algorithms for fault tolerant arrays

• Published in: Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems pp. 42 - 51
• Main Authors: Libeskind-Hadas, R., Shrivastava, N., Melhem, R.G., Liu, C.L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1992
• Subjects: Approximation algorithms; Computer architecture; Computer science; Degradation; Delay; Fault tolerance; Fault tolerant systems; Optical arrays; Runtime; Very large scale integration
• ISBN: 0818628375; 9780818628375
• ISSN: 1550-5774
• DOI: 10.1109/DFTVS.1992.224367

Considers the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable. Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. It is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that this algorithm is very effective.< >