An improved synthesis algorithm for multiplexor-based PGAs

The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use o...

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Bibliographic Details
Published in[1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 380 - 386
Main Authors Murgai, R., Brayton, R.K., Sangiovanni-Vincentelli, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Boolean functions
Circuit synthesis
Combinational circuits
Data structures
Electronics packaging
Equations
Libraries
Logic arrays
Network synthesis
Tree graphs
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ISBN9780818628221
0818628227
ISSN0738-100X
DOI10.1109/DAC.1992.227774

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Summary:The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given.< >
ISBN:9780818628221
0818628227
ISSN:0738-100X
DOI:10.1109/DAC.1992.227774