The rise of the 3rd dimension for system intergration

• Published in: Proceedings of the IEEE International Interconnect Technology Conference pp. 1 - 5
• Main Author: Beyne, E.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2006
• Subjects: Assembly; Electronics packaging; Integrated circuit interconnections; Integrated circuit technology; Passivation; Semiconductor device packaging; Stacking; Substrates; Tiles; Wiring
• ISBN: 1424401046; 9781424401048
• ISSN: 2380-632X
• DOI: 10.1109/IITC.2006.1648629

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP (`above' passivation), approach and a foundry level (`below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail