A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition

• Published in: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference pp. 1 - 4
• Main Authors: Guangji He, Sugahara, T., Izumi, S., Kawaguchi, H., Yoshimoto, M.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.09.2012
• Subjects: 40 nm VLSI; Field programmable gate arrays; hidden Markov model (HMM); Hidden Markov models; large vocabulary continuous speech recognition (LVCSR) 2.4; Random access memory; Real-time systems; Speech recognition; Very large scale integration; Viterbi algorithm
• ISBN: 9781467315555; 1467315559
• ISSN: 0886-5930
• DOI: 10.1109/CICC.2012.6330678

This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.