Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

• Published in: Proceedings 18th IEEE VLSI Test Symposium pp. 97 - 104
• Main Authors: Jing-Jia Liou, Kwang-Ting Cheng, Mukherjee, D.A.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2000
• Subjects: Circuit analysis computing; Circuit noise; Circuit optimization; Circuit testing; Delay; Information analysis; Performance analysis; Signal analysis; Timing; Virtual manufacturing
• ISBN: 9780769506135; 0769506135
• ISSN: 1093-0167
• DOI: 10.1109/VTEST.2000.843832

The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature. In order to capture the effects of these statistical variations on circuit performance, we incorporate statistical information in timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. We further propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure caused by the target type of defect, noise or variation source. This new path selection methodology defines a new path/segment searching paradigm for detecting delay faults in deep sub-micron devices.