Programmable design for memory sharing processor array

Memory sharing processor array (MSPA) architecture has been proposed with advantages of high efficiency parallel processing, less data storage requirement, and high-cost performance. MSPA design methodology has been developed with regular structure and systematic procedure. In this paper, programmab...

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Bibliographic Details
Published in1997 IEEE International Symposium on Circuits and Systems Vol. 3; pp. 2048 - 2051 vol.3
Main Authors Li, D., Kunjeda, H.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 22.11.2002
Subjects
Application specific integrated circuits
Communication system control
Costs
Data engineering
Digital-to-frequency converters
Electronic mail
Memory
Parallel processing
Resource management
Signal generators
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ISBN9780780335837
078033583X
DOI10.1109/ISCAS.1997.621558

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Summary:Memory sharing processor array (MSPA) architecture has been proposed with advantages of high efficiency parallel processing, less data storage requirement, and high-cost performance. MSPA design methodology has been developed with regular structure and systematic procedure. In this paper, programmable MSPA is proposed. It embeds not only MSPA architecture, but design procedure into silicon chips so that various applications can be performed with high speed.
ISBN:9780780335837
078033583X
DOI:10.1109/ISCAS.1997.621558