An Open-Source 4 \times 8 Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow

• Published in: IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
• Main Authors: Chen, Po-Han, Tsao, Charles, Raina, Priyanka
• Format: Conference Proceeding
• Language: English
• Published: IEEE 21.05.2023
• Subjects: CGRA; Hardware Accelerator; Memory Compiler; Open-Source; SkyWater
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS46773.2023.10182052

With the end of Dennard scaling, hardware specialization has been broadly adopted in computing systems to improve performance and energy-efficiency. However, specialized hardware deprecates soon after new algorithms are introduced. A coarse-grained reconfigurable array (CGRA) offers the programmability required for accommodating application changes, while still being more efficient than FPGAs and GPUs. This work presents a 4\times 8 CGRA created using an open-source agile hardware-compiler co-design framework. This is the first CGRA chip designed using the open-source SkyWater 130nm technology and OpenRAM memory compiler. We present the CGRA architecture, implementation results, and silicon validation results to verify the technology portability of agile hardware design framework.