FPGA Implementation of Raptor Coded DS-CDMA for Wireless Sensor Networks in Low SNR Regime

Reliable communications over a noisy channel have emerged as a severe challenge in the field of digital wireless communications. The proposed system addresses the high BER issue in AWGN channels in the Low SNR (LSNR) regime by combining the Raptor code with the DS-CDMA technique. This paper focuses...

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Bibliographic Details
Published in2022 2nd International Conference on Electronic and Electrical Engineering and Intelligent System (ICE3IS) pp. 258 - 263
Main Authors Farhan, Ikhlas M., Zaghar, Dhafer R., Abdullah, Hadeel N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 04.11.2022
Subjects
AWGN channels
CDMA
Codes
FPGA
Hardware
LDPC
Low SNR
LT code
Raptor
Rateless codes
Receivers
Transmitters
VHDL
Wireless sensor networks
WSN
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DOI10.1109/ICE3IS56585.2022.10010226

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Summary:Reliable communications over a noisy channel have emerged as a severe challenge in the field of digital wireless communications. The proposed system addresses the high BER issue in AWGN channels in the Low SNR (LSNR) regime by combining the Raptor code with the DS-CDMA technique. This paper focuses on the hardware implementation of the proposed system. The hardware implementation was implemented on FPGA because it has the advantage of flexibility over traditional ASIC implementation. The Quarts tool is used to synthesize the proposed system on FPGA Altera DE2 70 using VHDL. As can be found in the report of compilation, approximately 32421 logic elements of the 68,416 logic elements available (47%) and 97 pins of the available 622 pins (16%) were employed.
DOI:10.1109/ICE3IS56585.2022.10010226