A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion

• Published in: Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test pp. 1 - 4
• Main Authors: Shu, Shao-Yu, Lin, Chun-Hung, Yang, Ching-Yuan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18.04.2022
• Subjects: CMOS process; Frequency modulation; frequency synthesizer; Frequency synthesizers; Phase measurement; Phase noise; phase-locked loop (PLL); Power supplies; pulse-width to current converter (PWCC); spur suppression; Sub-Sampling PD/CP (SSPD/CP); sub-sampling phase locked loop (SSPLL); Very large scale integration
• ISSN: 2472-9124
• DOI: 10.1109/VLSI-DAT54769.2022.9768063

In this paper, a 5-GHz frequency synthesizer based on sub-sampling phased locked loop (SSPLL) using a pulse-width to current conversion (PWCC) circuit is presented. The proposed PWCC technique converting the pulse-width of input clock signal into a modulated output current is applied to improve the conventional sub-sampling phase detector and charge-pump. Implemented by 180 nm CMOS process, the proposed frequency synthesizer dissipates 15.52m W from a 1.8- V power supply. The operation frequency is from 4.7 GHz to 5.2 GHz under the channel width of 10 MHz. The measured output spurious tone is −45.7 dB and the phase noise performance is −128.22 dB/Hz at 10 MHz offset.