FPGA-Based Simulated Bifurcation Machine

• Published in: International Conference on Field-programmable Logic and Applications pp. 59 - 66
• Main Authors: Tatsumura, Kosuke, Dixon, Alexander R., Goto, Hayato
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2019
• Subjects: Bifurcation; Combinatorial optimization; Computational complexity; Field programmable gate arrays; FPGA; GPU; Graphics processing units; HLS; Ising problem; Optimization; Oscillators; Parallel processing; simulated annealing; simulated bifurcation
• ISSN: 1946-1488
• DOI: 10.1109/FPL.2019.00019

Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). The 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).