Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM

• Published in: Technical digest - International Electron Devices Meeting pp. 28.3.1 - 28.3.4
• Main Authors: Ye, H., Gomez, J., Chakraborty, W., Spetalnick, S., Dutta, S., Ni, K., Raychowdhury, A., Datta, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 12.12.2020
• Subjects: Field effect transistors; Leakage currents; Logic gates; Nonvolatile memory; Random access memory; Three-dimensional displays; Voltage control
• ISSN: 2156-017X
• DOI: 10.1109/IEDM13553.2020.9371981

We experimentally demonstrate W-doped amorphous In 2 O 3 double-gate field-effect transistors (DG IWO FET) with 5nm channel thickness and 50nm channel length exhibiting (a) excellent subthreshold slope (SS) of 73mV/dec, (b) record ID,SAT of 550μA/μm at V GS -V TH =2V, V DS =1V, and (c) high on-off ratio> 1x10 12 . 20nm gate length IWO DG FET was also fabricated to demonstrate scaling potential. We experimentally demonstrate IWO FET based capacitorless 2T gain cell embedded DRAM (eDRAM) ideal for monolithic 3D (M3D) integration exhibiting (a) cell level leakage current of ~1x10 -15 A/μm and ~1x10 -14 A/μm at 25C and 85C, (b) retention time 1s and 300ms at 25C and 85C respectively with effective storage node capacitance of 1 fF. Array level analysis of IWO capacitorless 2T eDRAM shows that access time <; 2ns is achievable with further scaling and moderate outside-the-rail voltages. M3D 2T eDRAM based on IWO FETs offers lower write time than embedded non-volatile random access memory (eNVRAM) and consumes 100x lower stand-by power and 1000x lower refresh power than conventional SRAM and eDRAM, respectively, making it an excellent candidate for fast and embedded memory with unlimited endurance.