Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets

• Published in: 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) pp. 226 - 238
• Main Authors: Verucchi, Micaela, Theile, Mirco, Caccamo, Marco, Bertogna, Marko
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2020
• Subjects: Benchmark testing; Computational modeling; DAG; Embedded systems; end-to-end latency; multi-rate; Parallel processing; Predictive models; Real-time systems; schedulability; Sensors
• ISSN: 2642-7346
• DOI: 10.1109/RTAS48715.2020.000-4

Modern automotive and avionics embedded systems integrate several functionalities that are subject to complex timing requirements. A typical application in these fields is composed of sensing, computation, and actuation. The ever increasing complexity of heterogeneous sensors implies the adoption of multi-rate task models scheduled onto parallel platforms. Aspects like freshness of data or first reaction to an event are crucial for the performance of the system. The Directed Acyclic Graph (DAG) is a suitable model to express the complexity and the parallelism of these tasks. However, deriving age and reaction timing bounds is not trivial when DAG tasks have multiple rates. In this paper, a method is proposed to convert a multi-rate DAG task-set with timing constraints into a single-rate DAG that optimizes schedulability, age and reaction latency, by inserting suitable synchronization constructs. An experimental evaluation is presented for an autonomous driving benchmark, validating the proposed approach against state-of-the-art solutions.