Performance analysis of on-chip bufferless router with multi-ejection ports

• Published in: Proceedings (International Conference on ASIC) pp. 1 - 4
• Main Authors: Chaochao Feng, Zhuofan Liao, Zhonghai Lu, Jantsch, Axel, Zhenyu Zhao
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.11.2015
• Subjects: Buffers; Conferences; Decision support systems; Ejection; Electronics; Hardware; Ports; Routers; Workload
• ISBN: 9781479984831; 1479984833
• ISSN: 2162-755X
• DOI: 10.1109/ASICON.2015.7517174

In general, the bufferless NoC router has only one local output port for ejection, which may lead to multiple arriving flits competing for the only one output port. In this paper, we propose a reconfigurable bufferless router in which the number of ejection ports can be configured as 2, 3 and 4. Simulation results demonstrate that the average packet latency of the routers with multi-ejection ports is 18%, 10%, 6%, 14%, 9% and 7% on average less than that of the router with 1 ejection ports under six synthetic workloads respectively. For application workloads, the average packet latency of the router with more than two ejection ports is slightly better than the router with only one ejection port, which can be neglect. Making a compromise of hardware cost and performance, it can be concluded that it is no need to implement bufferless routers with 3 and 4 ejection ports, as the router with 2 ejection ports can achieve almost the same performance as the routers with 3 and 4 ejection ports.