Algorithmic Time, Energy, and Power on Candidate HPC Compute Building Blocks

• Published in: Proceedings - IEEE International Parallel and Distributed Processing Symposium pp. 447 - 457
• Main Authors: Jee Choi, Dukhan, Marat, Xing Liu, Vuduc, Richard
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2014
• Subjects: Abstracts; Algorithm design and analysis; algorithms; Computational modeling; energy; Graphics processing units; Mobile communication; performance modeling; power; Power measurement; system balance
• ISBN: 1479937991; 9781479937998
• ISSN: 1530-2075
• DOI: 10.1109/IPDPS.2014.54

We conducted a micro benchmarking study of the time, energy, and power of computation and memory access on several existing platforms. These platforms represent candidate compute-node building blocks of future high-performance computing systems. Our analysis uses the "energy roofline" model, developed in prior work, which we extend in two ways. First, we improve the model's accuracy by accounting for power caps, basic memory hierarchy access costs, and measurement of random memory access patterns. Secondly, we empirically evaluate server-, mini-, and mobile-class platforms that span a range of compute and power characteristics. Our study includes a dozen such platforms, including x86 (both conventional and Xeon Phi), ARM, GPU, and hybrid (AMD APU and other SoC) processors. These data and our model analytically characterize the range of algorithmic regimes where we might prefer one building block to others. It suggests critical values of arithmetic intensity around which some systems may switch from being more to less time- and energy-efficient than others, it further suggests how, with respect to intensity, operations should be throttled to meet a power cap. We hope our methods can help make debates about the relative merits of these and other systems more quantitative, analytical, and insightful.