Background ADC calibration in digital domain

A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB a...

Full description

Saved in:
Bibliographic Details
Published in2008 IEEE Custom Integrated Circuits Conference pp. 301 - 304
Main Authors Cheongyuen Tsang, Yun Chiu, Vanderhaegen, J., Hoyos, S., Chen, C., Brodersen, R., Nikolic, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Calibration
CMOS analog integrated circuits
CMOS digital integrated circuits
CMOS technology
Digital filters
Error correction
Operational amplifiers
Pipelines
Transfer functions
Voltage
Online AccessGet full text
ISBN9781424420186
1424420180
ISSN0886-5930
DOI10.1109/CICC.2008.4672081

Cover

More Information
Summary:A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.
ISBN:9781424420186
1424420180
ISSN:0886-5930
DOI:10.1109/CICC.2008.4672081