Simulated annealing based thermal-aware floorplanning

As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a...

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Bibliographic Details
Published in2011 International Conference on Electronics, Communications and Control pp. 463 - 466
Main Authors Lixia Qi, Yinshui Xia, Lunyao Wang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2011
Subjects
Benchmark testing
Cost function
floorplanning
power density
Simulated annealing
SoC
Temperature distribution
thermal aware
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ISBN1457703203
9781457703201
DOI10.1109/ICECC.2011.6067654

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Summary:As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a simulated annealing based thermal-aware floorplanning for SoC design. The proposed method is applied to MCNC benchmark circuits, the results show that the temperature for MCNC hp can be reduced up to 23°C.
ISBN:1457703203
9781457703201
DOI:10.1109/ICECC.2011.6067654