ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs

• Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) pp. 259 - 264
• Main Authors: Hesham, Salma, Gohringer, Diana, Abd El Ghany, Mohamed
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2016
• Subjects: Field programmable gate arrays; Hardware; MPSoC; Networks-on-Chip; Quality of service; Real-time; Real-time systems; Switches; Time division multiplexing
• DOI: 10.1109/IPDPSW.2016.87

NoC-based MPSoCs are the fitting platform for the requirements of embedded and cyber physical systems. A significant expanse of these systems abides by real-time constraints which further add to the NoC design challenges. Several architectural solutions are presented in the literature targeting real-time NoCs, also referred to as quality of service (QoS) NoCs, however, they lack a common evaluation platform and performance criteria. In this paper, ARTNoCs is proposed as a hardware evaluation framework for real-time NoC architectures in a 2D mesh platform. The proposed framework supports different QoS router architectures in terms of switching control, ports structure, routing algorithm, flow-control and node latency. The framework offers a common hardware evaluation platform for the different router architectures over both FPGA and ASIC design flows, in addition to the latency and real-time performance evaluation under specified traffic scenarios. ARTNoCs is the first framework targeting real-time NoCs allowing the designer to compare and contrast different QoS router architectures on a reliable evaluation platform.