FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic

• Published in: 2015 Annual IEEE India Conference (INDICON) pp. 1 - 5
• Main Authors: Gangadari, Bhoopal Rao, Ahamed, Shaik Rafi
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Algorithms; Arithmetic; Composite Field Arithmetic (CFA); Construction; Electronics; Encryption; Field Programmable Gate Array (FPGA); Field programmable gate arrays; Gates; Hardware; Logic gates; Look Up Table (LUT); Mapping; Substitution Box (S-Box); Table lookup
• ISSN: 2325-9418
• DOI: 10.1109/INDICON.2015.7443745

This paper present method for constructions of the S-Box for Advanced Encryption Standard (AES) algorithm using composite field arithmetic in GF(((2 2 ) 2 ) 2 ). It is advantageous to implement the composite field arithmetic (CFA) on Field Programmable Gate Array for AES algorithm. Moreover, architectural implementation of S-Box using CFA reduces the hardware in terms of gates count as compared with that classical Look Up Table based S-Box for AES algorithm. The composite fields are constructed by decomposition methodology. However, an isomorphic mapping function to map the GF (2 8 ) representation to its composite field in GF (((2 2 ) 2 ) 2 ) and eight such mappings exist for each construction. The proposed CFA based S-Box implementation on hardware provides less area by 50% and low power consumption compared to the classical S-Box.