Replacement techniques for improving performance in sub-block caches

Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performa...

Full description

Saved in:
Bibliographic Details
Published inConference record - Asilomar Conference on Signals, Systems, & Computers pp. 1853 - 1857
Main Authors Olorode, Oluleye, Nourani, Mehrdad
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2014
Subjects
2
Benchmark testing
Computer architecture
Computers
Degradation
G. Architecture and Implementation
Hardware
Performance evaluation
Random access memory
Online AccessGet full text
ISSN1058-6393
DOI10.1109/ACSSC.2014.7094789

Cover

Abstract Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performance degradation due to cache pollution. We propose intelligent subblock cache replacement policies that use the valid state of individual sub-blocks in replacement decisions at the super-block level. Performance evaluations using Simplescalar toolset show improvement of up to 4.17% in SPEC2006 benchmarks.
AbstractList Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performance degradation due to cache pollution. We propose intelligent subblock cache replacement policies that use the valid state of individual sub-blocks in replacement decisions at the super-block level. Performance evaluations using Simplescalar toolset show improvement of up to 4.17% in SPEC2006 benchmarks.
Author Olorode, Oluleye
Nourani, Mehrdad
Author_xml – sequence: 1
  givenname: Oluleye
  surname: Olorode
  fullname: Olorode, Oluleye
  email: olorode@utdallas.edu
  organization: Dept. of Electr. Eng., Univ. of Texas at Dallas Richardson, Dallas, TX, USA
– sequence: 2
  givenname: Mehrdad
  surname: Nourani
  fullname: Nourani, Mehrdad
  email: nourani@utdallas.edu
  organization: Dept. of Electr. Eng., Univ. of Texas at Dallas Richardson, Dallas, TX, USA
BookMark eNotj8tOwzAURA0Cibb0B2DjH0i4dvxcVuEpVUKisK4c55oaEickKRJ_TxFdzBxpFkeaOTlLXUJCrhjkjIG9WZWbTZlzYCLXYIU29oQsrTZMaGsNtxJOyYyBNJkqbHFB5uP4AcCBGz4jty_YN85ji2miE_pdil97HGnoBhrbfui-Y3qnPQ6HoXXJI42Jjvsqq5rOf1Lv_A7HS3IeXDPi8sgFebu_ey0fs_Xzw1O5WmeRg5kyUwXw-tA-GK-AcVmjlJY7VweDoqq58MFVtnZKeVEbDEzKvzhQmitRLMj1vzci4rYfYuuGn-3xdPELMW1OkQ
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/ACSSC.2014.7094789
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 9781479982950
9781479982974
1479982954
1479982970
EISSN 1058-6393
EndPage 1857
ExternalDocumentID 7094789
Genre orig-research
GroupedDBID 29F
6IE
6IF
6IH
6IK
6IL
6IM
6IN
AAJGR
AAWTH
ABLEC
ACGFS
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
IJVOP
IPLJI
M43
OCL
RIE
RIL
RIO
RNS
ID FETCH-LOGICAL-i208t-8bf0c78bfcf8c60125de5592aadf8e4bd24cfab9da66c4d8ef155f155a0672643
IEDL.DBID RIE
IngestDate Wed Aug 27 02:07:40 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i208t-8bf0c78bfcf8c60125de5592aadf8e4bd24cfab9da66c4d8ef155f155a0672643
PageCount 5
ParticipantIDs ieee_primary_7094789
PublicationCentury 2000
PublicationDate 20141101
PublicationDateYYYYMMDD 2014-11-01
PublicationDate_xml – month: 11
  year: 2014
  text: 20141101
  day: 01
PublicationDecade 2010
PublicationTitle Conference record - Asilomar Conference on Signals, Systems, & Computers
PublicationTitleAbbrev ACSSC
PublicationYear 2014
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0020282
Score 1.8924296
Snippet Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power...
SourceID ieee
SourceType Publisher
StartPage 1853
SubjectTerms 2
Benchmark testing
Computer architecture
Computers
Degradation
G. Architecture and Implementation
Hardware
Performance evaluation
Random access memory
Title Replacement techniques for improving performance in sub-block caches
URI https://ieeexplore.ieee.org/document/7094789
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LS8NAEB5aT3rx0Ypv9uDRpDHZZjdHqZYiKEIt9Fb2NVAKabHJxV_vTtKmKh48JIRAHuzCfvPNzPctwG2MCdq-4oHmfgnkVvt1EDMMjEpSTFEQpFG3xWs6mvDnaX_agrtGC-Ocq5rPXEiXVS3fLk1JqbKe8FxEyKwNbSHTWqvVkCviDltRTJT1Hgbj8YA6t3i4eerH9ikVegwP4WX73bppZBGWhQ7N5y9Lxv_-2BF0dzo99tYg0DG0XH4CB98sBjvw6CNsypTTC1hj2LpmPlZl821Cga128gE2z9m61IH2KLdghvye112YDJ_eB6Ngs3NCMI8jWQRSY2SEPxuUxlOuuG-dpw6xUhal49rG3KDSmVVpariVDn1YQYeiyqwPUk5hL1_m7gxYmiHVdaNEo-B4HyktUGZOWm2SyKA9hw6Nx2xVm2PMNkNx8fftS9inOanFfFewV3yU7tqjeqFvqun8Al5JpOo
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LS8NAEB5qPagXH634dg8eTRqTTbI5SrVUbYvQFnor-xoohbTY5OKvdzdpUxUPHhJCIA92Yb_5Zub7FuDOxwBVyKkjqFkCqRJmHcQEHcmDCCOMLaTZbotB1B3T10k4qcF9pYXRWhfNZ9q1l0UtXy1kblNlrdhwkZglO7AbUkrDUq1V0SvLHjayGC9pPbaHw7bt3aLu-rkfG6gU-NE5hP7my2XbyNzNM-HKz1-mjP_9tSNobpV65L3CoGOo6fQEDr6ZDDbgycTYNlduX0Aqy9YVMdEqmW1SCmS5FRCQWUpWuXCEwbk5kdbxedWEced51O46670TnJnvscxhAj0Zm7NEJg3p8kOlDXnwOVfINBXKpxK5SBSPIkkV02gCC3twW5s1Ycop1NNFqs-ARAnayq4XCIwpPnhcxMgSzZSQgSdRnUPDjsd0WdpjTNdDcfH37VvY6476vWnvZfB2Cft2fkpp3xXUs49cXxuMz8RNMbVfLzqoNw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Conference+record+-+Asilomar+Conference+on+Signals%2C+Systems%2C+%26+Computers&rft.atitle=Replacement+techniques+for+improving+performance+in+sub-block+caches&rft.au=Olorode%2C+Oluleye&rft.au=Nourani%2C+Mehrdad&rft.date=2014-11-01&rft.pub=IEEE&rft.eissn=1058-6393&rft.spage=1853&rft.epage=1857&rft_id=info:doi/10.1109%2FACSSC.2014.7094789&rft.externalDocID=7094789