Replacement techniques for improving performance in sub-block caches

Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performa...

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Bibliographic Details
Published inConference record - Asilomar Conference on Signals, Systems, & Computers pp. 1853 - 1857
Main Authors Olorode, Oluleye, Nourani, Mehrdad
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2014
Subjects
2
Benchmark testing
Computer architecture
Computers
Degradation
G. Architecture and Implementation
Hardware
Performance evaluation
Random access memory
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ISSN1058-6393
DOI10.1109/ACSSC.2014.7094789

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Summary:Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performance degradation due to cache pollution. We propose intelligent subblock cache replacement policies that use the valid state of individual sub-blocks in replacement decisions at the super-block level. Performance evaluations using Simplescalar toolset show improvement of up to 4.17% in SPEC2006 benchmarks.
ISSN:1058-6393
DOI:10.1109/ACSSC.2014.7094789