A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operatio...

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Bibliographic Details
Published in2015 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2129 - 2132
Main Authors Terada, Kotaro, Yanagisawa, Masao, Togawa, Nozomu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2015
Subjects
Algorithm design and analysis
Clocks
Computer architecture
Delays
Registers
Schedules
Scheduling
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ISSN0271-4302
DOI10.1109/ISCAS.2015.7169100

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Summary:As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.
ISSN:0271-4302
DOI:10.1109/ISCAS.2015.7169100