ASIC/FPGA implementation of cochlear implant CIS algorithm based on FFT filter bank

• Published in: TENCON ... IEEE Region Ten Conference pp. 1 - 5
• Main Authors: Haichen Zhao, Xiong Deng, Qi Liang, Yixin Zhao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2013
• Subjects: CIS algorithm; cochlear implant; Cochlear implants; FFT; filter bank; Filter banks; Signal processing algorithms; Speech; Speech synthesis; Timing
• ISBN: 9781479928255; 1479928259
• ISSN: 2159-3442
• DOI: 10.1109/TENCON.2013.6718992

Speech processor is the key digital signal processor in a cochlear implant. The performance of the speech processing algorithm utilized by the speech processor is deeply relating the overall power dissipation, size and performances of the cochlear implant. CIS (Continuous Interleaved Sampling) algorithm is the most famous and used algorithm in the cochlear implant speech processing. This article uses a FFT (Fast Fourier Transform) filter bank instead of the traditional IIR (Infinite Impulse Response) or FIR (Finite Impulse Response) filter banks to process the speeches in frequency domain. It can easily switch the channels, and bring little extra consumption when increasing channels with the same FFT. A FPGA prototype is used for real speech timing simulations which prove the advantages of the design.