Chiplet based approach for heterogeneous processing and packaging architectures

• Published in: 2016 IEEE Aerospace Conference pp. 1 - 12
• Main Authors: Mounce, Gabriel, Lyke, Jim, Horan, Stephen, Doyle, Rich, Some, Rafi, Powell, Wes
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2016
• Subjects: Complexity theory; Computers; Integrated circuits; Multicore processing; NASA; Packaging
• DOI: 10.1109/AERO.2016.7500830

Creating integrated systems on-chip (SoCs) for aerospace platforms is becoming increasingly intractable in advanced semiconductor nodes (<; 90 nm) due to: (1) the expense of semiconductor processing and fabrication, (2) sheer complexity in terms of number of circuit elements for a large die, and (3) limited quantities of systems over which development costs can be amortized. To overcome some of these barriers, a modular "chiplet" motif is proposed around which a scalable and heterogeneous architecture multi-generational roadmap for microelectronics can be based that preserves many of the benefits of a SoC approach. A chiplet is defined as a small, high-performance nodal architecture that can be connected to other chiplets using a number of universal links for high-speed communications. The links can be either parallel or serial, each conveying the same information. Parallel links are used in multichip module / 2.5D packaging, in which a number of chiplets may be a packaged into a tightly coupled configuration (having in theory thousands of interconnects). Serial links are used in simpler forms of packaging to connect nodes across boards, backplanes, and boxes. The universality is important for two reasons. First, by establishing an equivalence between parallel and serial links, the same grouping of chips can be packaged in several different ways that result in functionally equivalent implementations (except that the inter-nodal latency will vary between parallel and serial connections). The performance of the links can be evolved over time to take advantage of the fastest available transport (including optical) or the widest parallel embodiments (for aggressive 3-D through-silicon via connections). Second, since the links only pass information, it is conceivable that node designs can be substantially different, allowing heterogeneous mixtures of chiplets, to include not only different embodiments of the same processor, but also wholly different classes of node types, to include ultradense memory "servers" (capable of managing multiple high-speed streams through the same link mechanisms), field programmable gate array (FPGA) clusters, and even extended to include complex, configurable analog and radiofrequency functional blocks in the future. By establishing standard messaging protocols, node arrangements can self-organize as more copies of different node types are added, creating a natural approach for building systems flexibly based on the best of breed semiconductor and packaging technologies. This paper will introduce the basic form of the chiplet concept inspired from joint AFRL/NASA work on next-generation space processing and previous work on scaled reconfigurable processing architectures, and describe some of the features we believe necessary to support scalability and heterogeneity with multi-domain, hybrid architectures involving a mixture of semiconductor technologies, transport concepts, and advanced packaging approaches.