Design and Implementation of a Delay-Based PUF for FPGA IP Protection

• Published in: 2013 International Conference on Computer-Aided Design and Computer Graphics pp. 107 - 114
• Main Authors: Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2013
• Subjects: Delays; EDA; Fabrication; fabrication variation; Field programmable gate arrays; fingerprint; FPGAs; hardware security; intellectual property (IP) protection; IP cores; Multiplexing; physical unclonable functions (PUFs); Random access memory; Shift registers; Table lookup; watermarking
• DOI: 10.1109/CADGraphics.2013.22

Physical Unclonable Function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA Intellectual Property (IP) protection, key generation and digital rights management. Ring Oscillator (RO) based PUF and Arbiter-based PUF are the most popular PUFs, but they are not specially designed for FPGA. RO-based PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ``hard macros'' to implement on FPGA. The arbiter-based PUF brings low resource overhead, but its structure is hard to be mapped on FPGA. Anderson'PUF can address these weaknesses of current Arbiter-based and RO-based PUFs. However, it cannot be directly implemented on the new generation FPGAs, and therefore it has the scalability issue. In order to address these problems, this paper presents a delay-based PUF using the intrinsic structure of FPGA (look-up table and multiplexer). The proposed delay-based PUF is completely realized on 28nm FPGAs. The experimental results show its high uniqueness and reliability. Moreover, we test the proposed PUF in the high temperature, and the results show its availability. Finally, the prospect of the proposed PUF in the FPGA IP protection is discussed.