Optimised AES with RISC-V Vector Extensions

• Published in: IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems pp. 57 - 60
• Main Authors: Rizi, Mahnaz Namazi, Zidaric, Nusa, Batina, Lejla, Mentens, Nele
• Format: Conference Proceeding
• Language: English
• Published: IEEE 03.04.2024
• Subjects: Acceleration; AES; Classic McEliece; Computers; Hardware; Instruction sets; Organizations; Quantum computing; RISC-V; Standards organizations; Vector Extensions; Vectors
• ISSN: 2473-2117
• DOI: 10.1109/DDECS60919.2024.10508919

With the advent of quantum computers, organizations and users should consider the potential impact of quantum threats on their cryptographic systems and be prepared to adopt Post-Quantum Cryptography (PQC) solutions when needed. However, PQC algorithms are often difficult to implement on standard processors and resource-constrained embedded devices, due to complicated mathematical algorithms and large parameters. The goal of this research is to design efficient HW/SW co-design of the PQC algorithm Classic McEliece (CM) using the RISC-V Instruction Set Architecture (ISA). In the first step, the acceleration of the AES algorithm, which is used as part of the key generation in CM, is explored using RISC-V Vector Extensions version 1.0 (RVV1.0). In this paper, we compare the vector-accelerated AES running on Vicuan coprocessor with the scalar AES running on Ibex.