Signal Agnostic Scalable Scan Wrapper Design

• Published in: VLSI design pp. 234 - 239
• Main Authors: H, Hanumantharaya, Veetil, Ratheesh T, Gadi, Anvesh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2023
• Subjects: Computer architecture; Computer bugs; core wrapping; IEEE P1500; Interconnect scan wrapper cells; Logic gates; Measurement; Microprocessors; SOC interconnect testing; Switches; TAM; Test access mechanism; test coverage; Very large scale integration
• ISSN: 2380-6923
• DOI: 10.1109/VLSID57277.2023.00056

With rapid growth in VLSI technology, SoC became more complex as more and more IP's or partitions are packed inside the SoC. Defect screening at every node inside the core/IP in SoC and its interface becomes a challenge. Various test methods are proposed for better test coverage in industry. One of the widely used and popular approaches is IEEE P1500[1] [2], which has a scalable architecture that comes with TAM (Test Access Mechanism) and enables the switching between internal and external core testing. IEEE P1500 test methodology suggests, the core/partition to be fully wrapped for internal and external testing. This process introduces silicon bugs if any test sensitive ports are wrapped. In this paper we propose a signal agnostic scalable wrapper architecture which helps core/partition to be fully wrapped without any restriction on ports which results in best coverage and ensures a bug free silicon. This paper also discusses the integration of the proposed architecture and design in SoC and its pattern generation flow. Finally, we compare the results with existing wrapper architecture[3] and demonstrate how the proposed architecture ensures bug free silicon with enhanced test coverage.