Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure

• Published in: IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
• Main Authors: Su, Liang-Ying, Huang, Shih-Hsu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 19.05.2024
• Subjects: Circuits and systems; Design methodology; engineering change order; hardware obfuscation; Hardware security; Logic design; Logic gates; Reverse engineering; reverse engineering attacks; spare cells; Timing; timing optimization
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS58744.2024.10558231

Utilizing gate camouflaging-based obfuscation is an effective method to protect ICs against reverse engineering attacks. Nonetheless, because camouflaged logic gates exhibit greater delays than standard logic gates, integrating camouflaged logic gates may potentially introduce timing violations. To ensure timing closure, this paper introduces a timing-driven design flow for incorporating camouflaged logic gates. For camouflaged logic gates that have been integrated into the gate-level netlist, we perform timing-driven placement to meet timing constraints. Additionally, we also insert camouflaged gates as spare cells for metal-only ECO. We have developed both a security-driven ECO algorithm and a timing ECO algorithm to maximize security under timing constraints by fully utilizing the timing slacks on non-critical paths. Experiment data show that, compared to previous design methodologies, the proposed approach can optimize security and achieve timing closure simultaneously.