Design of an ASIC-Based High Speed 32-bit Floating Point Adder

• Published in: 2021 International Conference on Applied Electronics (AE) pp. 1 - 4
• Main Authors: Deka, Debarshi, Kumar, Navaneeth, Pal, Dipankar
• Format: Conference Proceeding
• Language: English
• Published: University of West Bohemia 07.09.2021
• Subjects: ASIC; Barrel Shifter; Cadence Genus and Innovus; Compound Adder; Computational modeling; Computer vision; Delays; Denormalized and Mixed numbers; Far and Close Data Path Algorithm; Floating Point Adder; Hardware design languages; Imaging; Kogge-Stone Adder; Leading One Predictor (LOP); Machine learning; Normalized; Prediction algorithms
• ISSN: 1803-7232
• DOI: 10.23919/AE51540.2021.9542881

Advancements in machine-learning algorithms made it necessary to explore fast algorithms for Floating Point operations, addition being most commonly used complex operation involving significant delay and power-consumption. Applications include high-performance computer vision, imaging and deep-learning functions accelerated using dedicated hardware accelerators. This paper proposes a 32-bit Floating Point Adder based on the 'Far-and-Close-Data-Path-Algorithm' with added optimizations to give a better implementation in terms of overall minimum latency and improved accuracy for certain input cases. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.