Implicit Partial Product-LDPC Codes Using Free-Ride Coding

• Published in: IEEE International Conference on Communications (2003) pp. 2471 - 2476
• Main Authors: Ma, Xiao, Wang, Qianfan, Cai, Suihua, Xie, Xinglin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16.05.2022
• Subjects: Bit error rate; Encoding; Free-ride codes; LDPC codes; Parity check codes; Prediction algorithms; Product codes; Simulation; Upper bound
• ISSN: 1938-1883
• DOI: 10.1109/ICC45855.2022.9839082

In this paper, we propose a new construction of product codes, where the whole information array is protected row-by-row by a low-density parity-check (LDPC) code while only a portion of the information array is protected column-by-column by an algebraic code. The most distinguished feature of the proposed product code is that, thanks to the free-ride coding technique, the additional column check bits are transmitted implicitly rather than explicitly. The constructed codes are referred to as implicit partial product-LDPC codes, which have the same rates as the row component LDPC codes. The decoding algorithm can be divided into four stages, including decoding of the free-ride codes, first-round decoding of the row codes, decoding of the column codes, and second-round decoding of the row codes by exploiting the messages associated with those successfully decoded columns. To predict the extremely low error rate of the doubly-protected (by both the row code and the column code) information bits, we derive an approximate upper bound. The simulation results show that, with a (3,6)-regular LDPC code of length 1024 as the component code, the proposed product code can lower the word error rate (WER) from 10 −2 down to 10 −6 at the SNR around 2 dB. The numerical results also show that the doubly-protected information bits are more reliable, which can have a bit error rate (BER) down to 10 −15 at SNR around 2.6 dB as implied by the presented approximate upper bound.