High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor

Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. The algorithm involves complex time consuming computations in the leaves of the tree for each data instance. These computations involve a lot of parallelisms which can be exploited and im...

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Bibliographic Details
Published in2021 6th International Conference for Convergence in Technology (I2CT) pp. 1 - 6
Main Authors Antony, Ashin, A, Devi, Varghese, Kuruvilla
Format Conference Proceeding
LanguageEnglish
Published IEEE 02.04.2021
Subjects
FPGA
Hardware
Hardware Accelerator
Hoeffding Tree
Logic gates
Online Decision Trees
Parallel processing
Prediction algorithms
Table lookup
Throughput
Vegetation
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DOI10.1109/I2CT51068.2021.9418100

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Summary:Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. The algorithm involves complex time consuming computations in the leaves of the tree for each data instance. These computations involve a lot of parallelisms which can be exploited and implemented in a field programmable gate array to achieve speedup. This paper presents a hardware accelerator for Hoeffding tree algorithm with adaptive naive bayes predictor in the leaves. The proposed system is capable of accelerating data streams with both nominal and numeric attributes using minimum hardware resources for huge datasets. It is implemented on a Xilinx VC707 board based on Virtex-7 XC7VX485T field programmable gate array. The implemented system is about 9x faster than StreamDm(C++), a well known reference software implementation for the standard forest cover type dataset.
DOI:10.1109/I2CT51068.2021.9418100