On Leveraging Multi-threshold FinFETs for Design Obfuscation

• Published in: Proceedings / IEEE Computer Society Annual Symposium on VLSI pp. 108 - 113
• Main Authors: Patil, Vinay C, Kundu, Sandip
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2020
• Subjects: Camouflaging; FinFETs; Hardware; Hardware obfuscation; Integrated circuits; IP Protection; Logic functions; Logic gates; Multi-threshold Logic; SAT; Threshold voltage
• ISSN: 2159-3477
• DOI: 10.1109/ISVLSI49217.2020.00029

Reverse engineering has been increasingly used by malicious actors to steal valuable Intellectual Property, leading to a loss of revenue and potential compromise of security from pollution of the supply chain with counterfeits. IC camouflaging is a promising approach to counter reverse engineering attacks. In this work, we leverage the availability of multi-threshold FinFET transistors to facilitate camouflaging of logic cells. We propose cell designs, for 2-, 3- and 4-input gates, which realize various logic functions by utilizing different combinations of transistors with different threshold voltages. The structurally identical cells increase the effort needed by an attacker to reverse engineer the logic as the cell's functionality is not apparent from its layout. We explore de-obfuscation of a camouflaged netlist using SAT solver based approach and show that our designs can increase the deobfuscation effort by over 10x compared to limited camouflaging.