Cost-effective Resilient FPGA-based LDPC Decoder Architecture

• Published in: Proceedings / IEEE International On-Line Testing Symposium pp. 84 - 89
• Main Authors: Souza, Eduardo N. de, Nazar, Gabriel L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2019
• Subjects: Decoding; fault tolerance; Field programmable gate arrays; FPGA; LDPC; Parallel processing; Parity check codes; Redundancy; Resilience
• ISSN: 1942-9401
• DOI: 10.1109/IOLTS.2019.8854457

Low-Density Parity-Check (LDPC) codes have been used in many communication standards due to their capacity-approaching performance with feasible decoding architectures. Field-Programmable Gate Arrays (FPGAs) have been shown to be appropriate for the implementation of LDPC decoders, due to their ability to exploit the fine-grained parallelism found in such codes, as well as due to their reconfigurability, which allows to easily adapt the decoder to different codes. The susceptibility of FPGAs to faults affecting their configuration memories, however, demands specific fault tolerance strategies when these devices are used in harsh environments, such as aerospace applications, or even in ground-level critical systems. Thus, in this work we present a characterization of the behavior of LDPC decoders when subject to configuration errors and show that a single error can substantially degrade decoding performance, differently from what is observed in application-specific circuits. Based on this characterization, we propose a cost-effective fault tolerance scheme able to cope with faults in the FPGA fabric. Identifying the most critical components allowed reducing performance degradation by 89 % while only covering 55 % of their area.