Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor

• Published in: Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test pp. 1 - 4
• Main Authors: Lin, Hong-Ke, Lin, Pin-Han, Liu, Chih-Wei
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2020
• Subjects: Computer architecture; Generators; Hardware; Mathematical model; Parallel processing; Random access memory; Throughput
• ISSN: 2472-9124
• DOI: 10.1109/VLSI-DAT49148.2020.9196280

In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoch architecture [1] to reduce the area of FIFOs in the MDC processor. Since the input to the MDC FFT is not in natural order, we need to design a reorder circuit. We proposed a data-scheduling algorithm that allows the reorder circuit to use the least number of memory banks to achieve area reduction. Furthermore, we proposed a twiddle-factorgenerator circuit for the 2-epoch architecture. It can effectively reduce the number of twiddle factors that need to be stored. We designed different specifications of FFT processors using the method described in this paper, and then synthesized using the TSMC 90 nm CMOS technology high-Vt standard cell library. Our processors can operate above 450MHz and the throughput is P\cdot R, where P is the parallelism of hardware and the R is the operating frequency.