An area efficient modular arithmetic processor

• Published in: ASIC, 2003. Proceedings. 5th International Conference on Vol. 2; pp. 1273 - 1276 Vol.2
• Main Authors: Sun Yile, Wu Xingjun
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• ISBN: 0780378946; 078037889X; 9780780378940; 9780780378896
• ISSN: 1523-553X
• DOI: 10.1109/ICASIC.2003.1277448

RSA public-key cryptography and some other algorithms require various modular arithmetic operations. This paper presents an area efficient modular arithmetic processor. The operands can vary in size from 256 to 2048 bits. Optimized CIOS algorithm is introduced to speed up modular multiplication. At a maximum clock rate of 60 MHz, it takes 57 ms to complete a 1024-bit modular exponentiation. The core circuit without RAM contains 16000 gates and the whole area measures only 3.31 mm 2 in a 0.35 μm CMOS technology. As a coprocessor, it is suitable for embedded systems, especially in area-constrained environments such as smart cards.