Dynamically Reconfigurable Resource Efficient AES Implementation for IoT Applications

• Published in: IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
• Main Authors: Ruby, Abdelrahman M., Soliman, Shady M., Mostafa, Hassan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2020
• Subjects: AES; Clocks; Decryption; DPR; Encryption; Field programmable gate arrays; FPGA; Hardware; Heuristic algorithms; IoT
• ISBN: 9781728133201; 1728133203
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS45731.2020.9181276

Internet of Things (IoT) is the ability of things to share useful data among each other. It is becoming one of the most crucial technologies of our generation, however, one of its biggest challenges is security. In this paper, a design is proposed using Advanced Encryption Standard (AES) and the Dynamic Partial Reconfiguration (DPR) feature of the FPGA to tackle the security problem. AES-128 is used with 128-bit input data and 128-bit key. DPR is a new feature that allows utilizing the same hardware for different functions, which minimizes area and power needed by a system. The variants of the DPR are one round of encryption and one round of decryption. The proposed design offers low hardware and low power consuming cryptographic algorithm. The average reduction in resources consumed is 33% for encryption and 29% for decryption and energy utilization is decreased by 43.75%. The proposed work is tested on ZC702 evaluation board, synthesized and implemented using Vivado 2015.2.