VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis

• Published in: Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 1 - 7
• Main Authors: Esmaeilzadeh, Hadi, Ghodrati, Soroush, Gu, Jie, Guo, Shiyu, Kahng, Andrew B., Kim, Joon Kyung, Kinzer, Sean, Mahapatra, Rohan, Manasi, Susmita Dey, Mascarenhas, Edwin, Sapatnekar, Sachin S., Varadarajan, Ravi, Wang, Zhiang, Xu, Hanyang, Yatham, Brahmendra Reddy, Zeng, Ziqing
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2021
• Subjects: Computer architecture; Hardware; Machine learning; Machine learning algorithms; Planning; Space exploration; Systolic arrays
• ISSN: 1558-2434
• DOI: 10.1109/ICCAD51958.2021.9643449

This paper introduces VeriGOOD-ML, an automated methodology for generating Verilog with no human in the loop, starting from a high-level description of a machine learning (ML) algorithm in a standard format such as ONNX. The Verilog RTL is then translated through a back-end design flow to GDSII, driven by a design planning approach that is well tailored to the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build ML hardware: the TABLA platform uses a dataflow architecture that is well suited to non-DNN ML algorithms; the GeneSys platform, with a systolic array and a SIMD array, is optimized for implementing DNNs; and the Axiline approach synthesizes small ML algorithms by hardcoding the structure of the algorithm into hardware, thus trading off flexibility for performance and power. The overall approach explores the design space of platform configurations and Pareto-optimal-PPA back-end implementations to yield designs that represent different tradeoffs at the algorithmic level between area, power, performance, and execution time. The overall methodology, from architecture to back-end design to hardware implementation, is described in this paper, and the results of VeriGOOD-ML are demonstrated on a set of ML benchmarks.