Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

• Published in: IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
• Main Authors: Saha, Prasenjit, Ahmed, Salman, Kalluru, Hema Sai, Abbas, Zia
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2021
• Subjects: Approximate Computing; Approximation algorithms; CMOS; Leakage Power; Optimization; Particle swarm optimization; Process Variations; Propagation delays; Speech processing; Standard Cell Optimization; Temperature distribution; Transistor Sizing; Transistors; VLSI
• ISBN: 9781728192017; 1728192013
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS51556.2021.9401794

This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55 o C to 125 o C) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.