A Generic Modulo- (2^\pm\delta) Addition Algorithm via Two-Valued Digit Encoding
Modular adders are essential arithmetic components in Residue Number System (RNS)-based applications, including digital signal processing, cryptography, and machine learning. These applications consistently push the boundaries of dynamic range (DR) and operating frequency, making the design of effic...
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| Published in | Proceedings - Symposium on Computer Arithmetic pp. 85 - 92 |
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| Main Authors | , , , |
| Format | Conference Proceeding |
| Language | English |
| Published |
IEEE
04.05.2025
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| Subjects | |
| Online Access | Get full text |
| ISSN | 2576-2265 |
| DOI | 10.1109/ARITH64983.2025.00023 |
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| Abstract | Modular adders are essential arithmetic components in Residue Number System (RNS)-based applications, including digital signal processing, cryptography, and machine learning. These applications consistently push the boundaries of dynamic range (DR) and operating frequency, making the design of efficient generic modular adders a critical and evolving challenge. This paper presents a novel algorithm for modulo -(2^{n}\pm \delta) addition, where \delta is an integer within the range 0\leq\delta\leq 2^{n-1}-1 . The proposed approach leverages a two-valued digit (twit) for encoding the value of \pm\delta and uses a faithful representation of operands. In this representation, each operand is encoded as an n-bit unsigned number augmented by a twit value \{0,\pm\delta\} . The algorithm efficiently performs modular addition by speculating and adjusting the twit value in the addition result. When the result exceeds the modulus, it subtracts \mathrm{z}^{n}\pm\delta by ignoring the carry-out and adjusting the speculated twit value. This adjustment is achieved through an XOR operation between the carry-out and the speculated twit value, simplifying the modular reduction process. The proposed design has been synthesized for practical n (4\leq n\leq 16 using a FreePDK 45 nm process. The results demonstrate superior performance across key metrics such as delay, area, and power consumption compared to previous designs, highlighting the efficacy and scalability of the approach. |
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| AbstractList | Modular adders are essential arithmetic components in Residue Number System (RNS)-based applications, including digital signal processing, cryptography, and machine learning. These applications consistently push the boundaries of dynamic range (DR) and operating frequency, making the design of efficient generic modular adders a critical and evolving challenge. This paper presents a novel algorithm for modulo -(2^{n}\pm \delta) addition, where \delta is an integer within the range 0\leq\delta\leq 2^{n-1}-1 . The proposed approach leverages a two-valued digit (twit) for encoding the value of \pm\delta and uses a faithful representation of operands. In this representation, each operand is encoded as an n-bit unsigned number augmented by a twit value \{0,\pm\delta\} . The algorithm efficiently performs modular addition by speculating and adjusting the twit value in the addition result. When the result exceeds the modulus, it subtracts \mathrm{z}^{n}\pm\delta by ignoring the carry-out and adjusting the speculated twit value. This adjustment is achieved through an XOR operation between the carry-out and the speculated twit value, simplifying the modular reduction process. The proposed design has been synthesized for practical n (4\leq n\leq 16 using a FreePDK 45 nm process. The results demonstrate superior performance across key metrics such as delay, area, and power consumption compared to previous designs, highlighting the efficacy and scalability of the approach. |
| Author | Rahmati, Dara Sadr, Amirhossein Gorgin, Saeid Kim, Jungrae |
| Author_xml | – sequence: 1 givenname: Saeid surname: Gorgin fullname: Gorgin, Saeid email: me@sgorgin.com organization: Sungkyunkwan University,Department of Electrical and Computer Engineering,Republic of Korea – sequence: 2 givenname: Amirhossein surname: Sadr fullname: Sadr, Amirhossein email: a.sadr@ipm.ir organization: School of Computer Science, Institute for Research in Fundamental Sciences (IPM),Tehran,Iran – sequence: 3 givenname: Dara surname: Rahmati fullname: Rahmati, Dara email: d_rahmati@sbu.ac.ir organization: Shahid Beheshti University,Department of Computer Science and Engineering,Tehran,Iran – sequence: 4 givenname: Jungrae surname: Kim fullname: Kim, Jungrae email: dale40@skku.edu organization: Sungkyunkwan University,Department of Electrical and Computer Engineering,Republic of Korea |
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| Snippet | Modular adders are essential arithmetic components in Residue Number System (RNS)-based applications, including digital signal processing, cryptography, and... |
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| SubjectTerms | Adders Digital signal processing Dynamic range Encoding Generic adder Heuristic algorithms Machine learning Machine learning algorithms Modular addition Power demand Residue Number System (RNS) Scalability Signal processing algorithms Two-Valued Digit (Twit) |
| Title | A Generic Modulo- (2^\pm\delta) Addition Algorithm via Two-Valued Digit Encoding |
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