Signal Integrity Assessment of Stretchable Interconnects for Flexible Electronics System

• Published in: International Symposium on VLSI Design and Test pp. 1 - 6
• Main Authors: Bhatti, Gulafsha, Agrawal, Yash, Palaparthy, Vinay
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2024
• Subjects: Eye-diagram; Finite element analysis; Flexible electronics; parasitic extraction; Reliability; Signal integrity; signal integrity stretchable interconnect; Silver; Software; Strain; Substrates; System performance; Very large scale integration
• ISSN: 2768-0800
• DOI: 10.1109/VDAT63601.2024.10705698

Flexible electronics (FE) systems are in high demand for emerging applications such as wearable gadgets, flexible display, biomedical and human-machine interfaces. To provide stretchability to these systems, it becomes necessary to develop a stretchable interconnect on an elastomeric substrate. The stretchable interconnect needs to be highly efficient to maintain electrical connections between components under applied mechanical deformations. The geometrical structure rigorously affects the parasitics of the interconnect. An optimized interconnect structure leads to reduce in latency and power consumption and hence improve the reliability of the system. In this work, multiple interconnect structures such as straight (St), zigzag (Zz), serpentine (Sp), horseshoe (Hr), rectangle (Rt) and are compared using finite element analysis (FEA). The silver (Ag) material is used as interconnect. All the considered stretchable interconnect structures are subject to uniaxial applied strain. Electrical parameters viz. resistance (R), inductance (L) and capacitance (C) are extracted to assess electrical performance of the interconnect. The novel contribution of this paper contains the eye-diagram analysis of the multiple stretchable interconnect structures under different applied strain conditions. Eye-diagram is an important tool for analyzing signal integrity effects. The several performance analyses have been performed in ANSYS and Cadence EDA tools.